1. Technical Field
The disclosure of the present invention generally relates to a non-volatile memory (NVM) device and the method for fabricating the same, and more particularly to a vertical channel memory and the method for fabricating the same.
2. Description of the Related Art
An NVM device which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell has been widespreadly adopted by bulk solid state memory applications in the art. A flash memory is a typical NVM device having charge storage structure, such as floating gate or dielectric charge trapping layer, configured in memory cells. Data is stored in the memory cells by control the volume of charge trapped in the charge storage structure, and the data stored in the memory cells may be associated with a threshold voltage of the memory cells contributed by the volume of the trapped charge.
In comparison with a floating gate flash memory, a charge trapping flash memory, e.g. a flash memory having a silicon-oxide-nitric-oxide-silicon (SONOS) structure, the advantages of better data retention, lower operating voltage, thinner thickness and capable of being integrated in an embedded system. Currently, it is preferable to use memory cells with dielectric charge trapping layer as the major basic elements for configuring a vertical channel flash memory. However, the operation reliability of the vertical channel flash memory may be deteriorated by the influence of edge and corner effect due to the non-uniform distribution of the charge stored in the dielectric charge trapping layer during the program/erase operation. And these problems may get worse as the critical dimensions continue to shrink.
In addition, the method for fabricating a traditional vertical channel flash memory generally includes steps as follows: A multilayers stack configured by a plurality of insulating layers and a plurality of poly-silicon layers alternatively stacked with each other is firstly provided. At least one through hole or trench is then formed in the multilayers stack, and a SONOS memory layer and a channel layer are formed in sequence on the sidewalls of the through hole/trench, whereby a plurality of memory cells are defined at the intersection points formed by the SONOS memory layer, the channel layer and the poly-silicon layers.
However, because the insulating layers and the poly-silicon layers have very different intrinsic properties, for example the removing rate of the insulating layers may be rather different from that of the poly-silicon layers during the etching process to form the through hole/trench. The etching profile of the through hole/trench formed by the etching process performed on the multilayers stack may be tapered, and the etch depth may be limited by the taper profile. As a result, the process windows of the vertical channel flash memory can be reduced significantly and will lead to yield loss. The memory capacity of the vertical channel flash memory thus can be rather constrained.
Therefore, there is a need of providing a memory device and the method for fabricating the same to obviate the drawbacks encountered from the prior art.